Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Breakpoint (BKP) Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Breakpoint (BKP) Module
BKBDM — Breakpoint Background Debug Mode Enable
This bit determines if the breakpoint causes the part to enter
Background Debug Mode (BDM) or initiate a Software Interrupt (SWI)
0 = Go to Software Interrupt on a compare.
1 = Go to BDM on a compare.
BKTAG — Breakpoint on Tag
This bit controls whether the breakpoint will cause a break on the next
instruction boundary (force) or on a match that will be an executable
opcode (tagged). Non-executed opcodes cannot cause a tagged
breakpoint
0 = On match, break at the next instruction boundary (force).
1 = On match, break if the match is an instruction that will be
executed (tagged).
Breakpoint Control
Register 1
(BKPCT1)
This register is used to control the breakpoint logic that resides within the
Core.
Read and write: anytime.
BK0MBH:BK0MBL — Breakpoint Mask High Byte and Low Byte for First
Address
In Dual or Full Mode, these bits may be used to mask (disable) the
comparison of the high and low bytes of the first address breakpoint.
(See Table 124.).
Address $__01
Bit 7 654321Bit 0
Read:
BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW
Write:
Reset: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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