Datasheet

Background Debug Module
MC9S12DP256 — Revision 1.1
Background Debug Module (BDM)
Figure 141 BDM Target-to-Host Serial Bit Timing (Logic 0)
Instruction Tracing When a TRACE1 command is issued to the BDM in active BDM, the
CPU exits the standard BDM firmware and executes a single instruction
in the user code. Once this has occurred, the CPU is forced to return to
the standard BDM firmware and the BDM is active and ready to receive
a new command. If the TRACE1 command is issued again, the next user
instruction will be executed. This facilitates stepping or tracing through
the user code one instruction at a time.
If an interrupt is pending when a TRACE1 command is issued, the
interrupt stacking operation occurs but no user instruction is executed.
Once back in standard BDM firmware execution, the program counter
points to the first instruction in the interrupt service routine.
Instruction
Tagging
The instruction queue and cycle-by-cycle CPU activity are
reconstructible in real time or from trace history that is captured by a
logic analyzer. However, the reconstructed queue cannot be used to
stop the CPU at a specific instruction, because execution already has
begun by the time an operation is visible outside the system. A separate
instruction tagging mechanism is provided for this purpose.
EARLIEST
START OF
NEXT BIT
CLOCK
TARGET SYS.
HOST
DRIVE TO
BKGD PIN
BKGD PIN
PERCEIVED
START OF BIT TIME
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
TARGET SYS.
DRIVE AND
SPEEDUP PULSE
SPEEDUP PULSE
HIGH-IMPEDANCE
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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