Datasheet

Background Debug Module (BDM)
Operation
MC9S12DP256 — Revision 1.1
Background Debug Module (BDM)
Figure 140 BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 141 shows the host receiving a logic 0 from the target. Since the
host is asynchronous to the target, there is up to a one clock-cycle delay
from the host-generated falling edge on BKGD to the start of the bit time
as perceived by the target. The host initiates the bit time but the target
finishes it. Since the target wants the host to receive a logic 0, it drives
the BKGD pin low for 13 target clock cycles then briefly drives it high to
speed up the rising edge. The host samples the bit level about 10 target
clock cycles after starting the bit time.
HIGH-IMPEDANCE
EARLIEST
START OF
NEXT BIT
R-C RISE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
PERCEIVED
START OF BIT TIME
BKGD PIN
CLOCK
TARGET SYSTEM
HOST
DRIVE TO
BKGD PIN
TARGET SYSTEM
SPEEDUP
PULSE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
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Freescale Semiconductor, Inc.
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