Datasheet

Background Debug Module
MC9S12DP256 — Revision 1.1
Background Debug Module (BDM)
Figure 139 BDM Host-to-Target Serial Bit Timing
The receive cases are more complicated. Figure 140 shows the host
receiving a logic 1 from the target system. Since the host is
asynchronous to the target, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit
time in the target. The host holds the BKGD pin low long enough for the
target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse
seven target clock cycles after the perceived start of the bit time. The
host should sample the bit level about 10 target clock cycles after it
started the bit time.
EARLIEST
START OF
NEXT BIT
TARGET SENSES BIT
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
CLOCK
TARGET SYSTEM
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED
START OF BIT TIME
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