Datasheet

Background Debug Module
MC9S12DP256 — Revision 1.1
Background Debug Module (BDM)
and resume execution of the user code. Disturbing the BDM shift register
prematurely may adversely affect the exit from the standard BDM
firmware lookup table.
Figure 138 represents the BDM command structure. The command
blocks illustrate a series of eight bit times starting with a falling edge. The
bar across the top of the blocks indicates that the BKGD line idles in the
high state. The time for an 8-bit command is 8 × 16 target clock cycles.
Figure 138 BDM Command Structure
BDM Serial
Interface
The BDM communicates with external devices serially via the BKGD pin.
During reset, this pin is a mode select input which selects between
normal and special modes of operation. After reset, this pin becomes the
dedicated serial interface pin for the BDM.
The BDM serial interface is timed using the clock selected by the
CLKSW bit in the status register (see BDM Status Register (BDMSTS)).
This clock will be referred to as the target clock in the following
explanation.
HARDWARE
HARDWARE
FIRMWARE
FIRMWARE
GO,
32-TC
TC = TARGET CLOCK CYCLES
COMMAND ADDRESS
150-TC
DELAY
NEXT
DELAY
8 BITS
AT ~16 TC/BIT
16 BITS
AT ~16 TC/BIT
16 BITS
AT ~16 TC/BIT
COMMAND ADDRESS DATA
NEXT
DATA
READ
WRITE
READ
WRITE
TRACE
COMMAND
NEXT
COMMAND DATA
64-TC
DELAY
NEXT
COMMAND
150-TC
DELAY
32-TC
DELAY
COMMAND
COMMAND
COMMAND
COMMAND
DATA
NEXT
COMMAND
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Freescale Semiconductor, Inc.
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