Datasheet

Background Debug Module (BDM)
Operation
MC9S12DP256 — Revision 1.1
Background Debug Module (BDM)
BDM Command
Structure
Hardware and firmware BDM commands start with an 8-bit opcode
followed by a 16-bit address and/or a 16-bit data word depending on the
command. All the read commands return 16 bits of data despite the byte
or word implication in the command name.
NOTE: 8-bit reads return 16-bits of data, of which, only one byte will contain
valid data. If reading an even address, the valid data will appear in the
MSB. If reading an odd address, the valid data will appear in the LSB.
NOTE: 16-bit misaligned reads and writes are not allowed. If attempted, the
BDM will ignore the least significant bit of the address and will assume
an even address from the remaining bits.
For hardware data read commands, the external host must wait 150
target clock cycles
1
after sending the address before attempting to
obtain the read data. This is to be certain that valid data is available in
the BDM shift register, ready to be shifted out. For hardware write
commands, the external host must wait 150 target clock cycles after
sending the data to be written before attempting to send a new
command. This is to avoid disturbing the BDM shift register before the
write has been completed. The 150 target clock cycle delay in both
cases includes the maximum 128 cycle delay that can be incurred as the
BDM waits for a free cycle before stealing a cycle.
For firmware read commands, the external host must wait 32 target
clock cycles after sending the command opcode before attempting to
obtain the read data. This allows enough time for the requested data to
be made available in the BDM shift register, ready to be shifted out. For
firmware write commands, the external host must wait 32 target clock
cycles after sending the data to be written before attempting to send a
new command. This is to avoid disturbing the BDM shift register before
the write has been completed.
The external host should wait 64 target clock cycles after a TRACE1 or
GO command before starting any new serial command. This is to allow
the CPU to exit gracefully from the standard BDM firmware lookup table
1. Target clock cycles are cycles measured using the target system’s serial clock rate. See BDM
Serial Interface and BDM Status Register (BDMSTS) for information on how serial clock rate is
selected.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...