Datasheet

Background Debug Module
MC9S12DP256 — Revision 1.1
Background Debug Module (BDM)
cleared when the next BDM command has been received or BDM is
exited. SDV is used by the standard BDM firmware to control program
flow execution.
1 = Data phase of command is complete
0 = Data phase of command not complete
TRACE — TRACE1 BDM firmware command is being executed
This bit gets set when a BDM TRACE1 firmware command is first
recognized. It will stay set as long as continuous back-to-back
TRACE1 commands are executed. This bit will get cleared when the
next command that is not a TRACE1 command is recognized.
1 = TRACE1 command is being executed
0 = TRACE1 command is not being executed
CLKSW — Clock switch
The CLKSW bit controls which clock the BDM operates with. It is only
writable from a hardware BDM command. A 150 cycle delay at the
clock speed that is active during the data portion of the command will
occur before the new clock source is guaranteed to be active. The
start of the next BDM command uses the new clock for timing
subsequent BDM communications.
1 = BDM system operates with bus rate
0 = BDM system operates with alternate clock
WARNING: Care must be taken when CLKSW=0 to ensure that the alternate clock
frequency does not exceed that of the bus clock frequency. The BDM will
not operate correctly if this condition exists.
UNSEC — Unsecure
This bit is only writable in special single chip mode from a hardware
BDM command and always gets reset to zero. It is in a zero state as
secure mode is entered so that the secure BDM firmware lookup table
is enabled and put into the memory map along with the standard BDM
firmware lookup table.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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