Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Background Debug Module (BDM)
Registers
MC9S12DP256 — Revision 1.1
Background Debug Module (BDM)
– ENBDM should only be set via a BDM hardware command if
the BDM firmware commands are needed. (This does not
apply in Special Single Chip Mode).
ENBDM — Enable BDM
This bit controls whether the BDM is enabled or disabled. When
enabled, BDM can be made active to allow firmware commands to be
executed. When disabled, BDM cannot be made active but BDM
hardware commands are still allowed.
1 = BDM enabled
0 = BDM disabled
NOTE:
ENBDM is set by the firmware immediately out of reset in special
single-chip mode.
BDMACT — BDM active status
This bit becomes set upon entering BDM. The standard BDM
firmware lookup table is then enabled and put into the memory map.
BDMACT is cleared by a carefully timed store instruction in the
standard BDM firmware as part of the exit sequence to return to user
code and remove the BDM memory from the map.
1 = BDM active
0 = BDM not active
ENTAG — Tagging enable
This bit indicates whether instruction tagging in enabled or disabled.
It is set when the TAGGO command is executed and cleared when
BDM is entered. The serial system is disabled and the tag function
enabled 16 cycles after this bit is written. BDM cannot process serial
commands while tagging is active.
1 = Tagging enabled
0 = Tagging not enabled, or BDM active
SDV — Shift data valid
This bit is set and cleared by the BDM hardware. It is set after data
has been transmitted as part of a firmware read command or after
data has been received as part of a firmware write command. It is
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