Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Byte Data Link Controller Module
Interrupt Operation
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Interrupt Operation
The BDLC will generate an Interrupt Request to the CPU when a BDLC
interrupt source is pending in the DLCBSVR. All DLCBSVR interrupts
except the Wakeup Interrupt (DLCBSVR=$20) can be masked by
clearing the IE bit in DLCBCR1. Refer to BDLC State Vector Register
(DLCBSVR) for a description of the BDLC interrupt sources and how to
service them.
Low Power Options
The BDLC can save power in Disabled, Wait, and Stop modes. A
complete description of what the BDLC does while in a low power mode
can be found in Modes of Operation.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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