Datasheet

Byte Data Link Controller Module
Modes of Operation
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
bit in the DLCBCR1 register is previously cleared. In this mode, the
BDLC internal clocks continue to run. Any activity on the J1850 network
will cause the BDLC to exit BDLC Wait mode and generate an
unmaskable interrupt of the CPU. This Wakeup interrupt state is
reflected in the DLCBSVR, encoded as the highest priority interrupt. This
interrupt can be cleared by the CPU with a read of the DLCBSVR.
Wakeup from
BDLC Wait with
CPU in WAIT
If the CPU executes the WAIT instruction and the BDLC enters the WAIT
mode (WCM = 0), the clocks to the BDLC as well as the clocks in the
MCU continue to run. Therefore, the message which wakes up the
BDLC from WAIT and the CPU from WAIT mode will also be received
correctly by the BDLC. This is because all of the required clocks
continue to run in the BDLC in WAIT mode.The wakeup behavior of the
BDLC applies regardless of whether the BDLC is in normal or 4X mode
when the WAIT instruction is executed.
BDLC Stop This power conserving mode is automatically entered from the Run
mode whenever the CPU executes a STOP instruction, or if the CPU
executes a WAIT instruction and the WCM bit in the DLCBCR1 register
is previously set. In this mode, the BDLC internal clocks are stopped.
Any activity on the network will cause the BDLC to exit BDLC Stop mode
and generate an unmaskable interrupt of the CPU. This Wakeup
interrupt state is reflected in the DLCBSVR, encoded as the highest
priority interrupt. This interrupt can be cleared by the CPU with a read of
the DLCBSVR. Depending upon which low-power mode instruction the
CPU executes to cause the BDLC to enter BDLC Stop, the message
which wakes up the BDLC (and the CPU) may or may not be received.
There are two different possibilities, both of which is described below.
These descriptions apply regardless of whether the BDLC is in normal
or 4X mode when the STOP or WAIT instruction is executed.
Wakeup from
BDLC Stop with
CPU in STOP
When the CPU executes the STOP instruction, all clocks in the MCU,
including clocks to the BDLC, are turned off. Therefore, the message
which wakes up the BDLC and the CPU from STOP mode will not be
received. This is due primarily to the amount of time required for the
MCU’s oscillator to stabilize before the clocks can be applied internally
to the other MCU modules, including the BDLC.
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