Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
and some MCU reset source is asserted. To prevent the BDLC from
entering an unknown state, the internal MCU reset is asserted while
powering up the BDLC. BDLC Reset mode is also entered from any
other mode as soon as one of the MCU’s possible reset sources (e.g.
LVR, POR, COP watchdog, Reset pin etc.) is asserted.
In this mode, the internal BDLC voltage references are operative, V
dd
is
supplied to the internal circuits, which are held in their reset state and the
internal BDLC system clock is running. Registers will assume their reset
condition. Outputs are held in their programmed Reset state, inputs and
network activity are ignored.
BDLC Disabled This mode is entered from the Reset mode after all MCU reset sources
are no longer asserted. It is entered from the Run mode whenever the
BDLCE bit in the DLCSCR register is cleared.
In this mode the mux interface clock (f
bdlc
) is stopped to conserve power
and allow the BDLC to be configured for proper operation on the J1850
bus. The IP bus interface clocks are left running in this mode to allow
access to all BDLC registers for initialization.
Run This mode is entered from the BDLC Disabled mode when the BDLCE
bit in the DLCSCR register is set. It is entered from the BDLC Wait mode
whenever activity is sensed on the J1850 bus or some other MCU
source wakes the CPU out of Wait mode.
It is entered from the BDLC Stop mode whenever network activity is
sensed or some other MCU source wakes the CPU out of Stop mode.
Messages will not be received properly until the clocks have stabilized
and the CPU is also in the Run mode.
In this mode, normal network operation takes place. The user should
ensure that all BDLC transmissions have ceased, by reading the IDLE
bit in the DLCBSTAT register, before exiting this mode.
BDLC Wait This power conserving mode is automatically entered from the Run
mode whenever the CPU executes a WAIT instruction and if the WCM
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Freescale Semiconductor, Inc.
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