Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link Controller Module
Modes of Operation
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Figure 135 BDLC Operating Modes State Diagram
Power Off This mode is entered from the Reset mode whenever the BDLC supply
voltage V
dd
drops below its minimum specified value for the BDLC to
guarantee operation. The BDLC will be placed in the Reset mode by a
system Low Voltage Reset (LVR) before being powered down. In this
mode, the pin input and output specifications are not guaranteed.
Reset This mode is entered from the Power Off mode whenever the BDLC
supply voltage V
dd
rises above its minimum specified value (V
dd(MIN)
)
V
dd
> V
dd
(Min.) and
Power Off
Reset
BDLC Stop
Run
V
dd
≤ V
dd
(Min.)
STOP instruction or
(from any mode)
BDLC Wait
Network activity or
(WAIT instruction and WCM=1)
(WAIT instruction and WCM=0)
Any MCU reset source asserted
No MCU reset source asserted
Any MCU reset source asserted
Network activity or
other MCU wake-up
other MCU wake-up
BDLCE cleared in DLCSCR register
BDLC
BDLCE set in DLCSCR register
Disabled
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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