Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Receiving A
Message In 4X
Mode
In a diagnostic or production environment large amounts of data may
need to be downloaded across the network to a component or module.
This data is often sent in a large “Block Mode” message (see above)
which violates the SAE J1850 limit for message length. In order to speed
up the downloading of these large blocks of data, they are sometimes
transmitted at four times (4X) the normal bit rate for the Variable Pulse
Width modulation version of SAE J1850. This higher speed
transmission, nominally 41.6kbps, allows these large blocks to be
transmitted much more quickly.
The BDLC is designed to receive (but not transmit) messages
transmitted at this higher speed. By setting the RX4XE bit in DLCBCR2,
the user can command the BDLC to receive any message sent over the
network at a 4X rate.
If the BDLC is placed in this 4X mode, messages transmitted at the
normal bit rate will not be received correctly. Likewise, 4X messages
transmitted on the SAE J1850 bus when the BDLC is in normal mode will
be interpreted as noise on the network by the BDLC. The RX4XE bit is
not affected by entry or exit from BDLC stop or wait modes. For more
information on the RX4XE bit, refer to RX4XE — Receive 4X Enable (Bit
5).
Modes of Operation
The BDLC has 6 main modes of operation which interact with the power
supplies, pins, and the rest of the MCU as shown below. The operation
of the BDLC in Normal and Special Modes are described later in this
section.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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