Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link Controller Module
Special BDLC Operations
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Receiving IFR
Exceptions
This basic IFR receiving flow can be interrupted for the same reasons as
a normal message reception. The IFR receiving process can be
adversely affected due to a CRC error, an Invalid or Out of Range
Symbol or due to a receiver overrun caused by the CPU failing to service
an RxIFR interrupt in a timely fashion. For a description of how these
exceptions can affect the IFR receiving process, refer to Receiving
Exceptions.
Special BDLC Operations
There are a few special operations which the BDLC can perform. What
follows is a brief description of each of these functions and when they
might be used.
Transmitting Or
Receiving A Block
Mode Message
The BDLC, because it handles each message on a byte-by-byte basis,
has the inherent capability of handling messages any number of bytes in
length. While during normal operation this requires the user to carefully
monitor message lengths to ensure compliance with SAE J1850
message limits, often in a production or diagnostic environment
messages which exceed the SAE J1850 limits can be beneficial. This is
especially true when large amounts of configuration data need to be
downloaded over the SAE J1850 network.
Because of the BDLC’s architecture, it can both transmit and receive
messages of unlimited length. The CRC calculations, both for
transmitting and receiving, are not limited to eight bytes, but will instead
be calculated and verified using all bytes in the message, regardless of
the number. All control bits, including TEOD and IMSG, also work in an
identical manner, regardless of the length of the message.
To transmit or receive these “Block Mode” messages, no extra BDLC
control functions must be performed. The user simply transmits or
receives as many bytes as desired in one message frame, and the
BDLC will operate just as if a message of normal length was being used.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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