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Byte Data Link Controller Module
Receiving An In-Frame Response (IFR)
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Receiving An In-Frame Response (IFR)
Receiving an In-Frame Response with the BDLC is very similar to
receiving a message frame. As each byte of an IFR is received, the
DLCBSVR will indicate this to the CPU. An EOF indication in the
DLCBSVR indicates that the IFR (and message) is complete. Also, the
IMSG bit can also be used to command the BDLC to mask any further
network activity from the CPU, including IFR bytes being received, until
the next valid SOF is received.
NOTE:
As with a message transmission, the IMSG bit should never be used to
ignore the BDLC’s own IFR transmissions. This is again due to the
DLCBSVR bits being inhibited from updating until IMSG is cleared,
preventing the CPU from detecting any IFR-related state changes which
may be of interest.
Receiving an IFR
with the BDLC
Receiving an IFR from the SAE J1850 bus requires the same procedure
that receiving a message does, except that as each byte is received the
Received IFR Byte (RxIFR) state is indicated in the DLCBSVR. All other
actions are the same. For an illustration of the steps described below,
refer to Receiving An IFR With the BDLC.
Step 1: When RxIFR
Interrupt Occurs,
Retrieve IFR Byte
When the first byte of an IFR following a valid EOD symbol is received
that byte is placed in the DLCBDR, and an RxIFR state is reflected in the
DLCBSVR. No indication of the EOD reception in made, since the RxIFR
state will indicate that the main portion of the message has ended and
the IFR portion has begun.
The RxIFR interrupt is cleared when the received IFR byte is read from
the DLCBDR. Once this is done, no further CPU intervention is
necessary until the next IFR byte is received, and this step is repeated.
As with a message reception, all bytes of the IFR, including the CRC
byte, will be placed into the DLCBDR as they are received for the CPU
to retrieve.
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