Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
last byte is written to the BDR, the TEOD bit is set, and a CRC byte (if
desired) and an EOD are then transmitted. Because the two versions of
the Type 3 IFR are transmitted identically, the description which follows
will discuss both. For an illustration of the Type 3 IFR transmit sequence,
refer to Transmitting A Type 3 IFR.
Step 1: Load the
First IFR Byte into
the DLCBDR
The user begins initiation of a Type 3 IFR, as with each of the other IFR
types, by loading the desired IFR byte into the DLCBDR. If a byte has
already been written into the DLCBDR for transmission as a new
message, the user can simply write the first IFR byte to the DLCBDR,
replacing the previously written byte. This must be done before the first
EOD symbol is received.
Step 2: Set the
TMIFR Bit
The second step necessary for transmitting a Type 3 IFR is to set the
desired TMIFR bit in DLCBCR2, depending upon whether or not a CRC
is desired. As previously described in BDLC IFR Transmit Control Bits,
the TMIFR1 bit should be set if the user requires a CRC byte to be
appended following the last byte of the Type 3 IFR, and TMIFR0 if no
CRC byte is required.
Setting the TMIFR1 or TMIFR0 bit will direct the BDLC to transmit the
byte in the BDR as the first byte of a single or multi-byte IFR preceded
by the appropriate Normalization Bit. Once this has occurred, the
DLCBSVR will reflect that the next byte of the IFR can be written to the
DLCBDR (TDRE interrupt).
The user must set the TMIFR1 or TMIFR0 bit before the EOD following
the main part of the message frame is received, or no IFR transmit
attempts will be made for the current message. If another node does
transmit an IFR to this message or a reception error occurs, the TMIFR1
or TMIFR0 bit will be cleared. If not, the IFR will be transmitted after the
EOD of the next received message.
Step 3: When TDRE
is Indicated, Write
the Next IFR Byte
into the DLCBDR
When a TDRE state is reflected in the DLCBSVR, the CPU writes the
next IFR byte to be transmitted into the DLCBDR, clearing the TDRE
interrupt. This step is repeated until the last IFR byte to be transmitted is
written to the DLCBDR.
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Freescale Semiconductor, Inc.
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