Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Step 2: Set the
TSIFR Bit
The second step necessary for transmitting a Type 2 IFR is to set the
TSIFR bit in DLCBCR2. Setting this bit will direct the BDLC to attempt to
transmit the byte in the DLCBDR as an IFR until it is successful. If the
byte is transmitted successfully, or if an error or loss of arbitration
occurs, TSIFR will be cleared and no further transmit attempts will be
made.
Step 3: If
Necessary, Set the
TEOD Bit
The third step in transmitting a Type 2 IFR is only necessary if the user
wishes to halt the transmission attempts. This may be necessary if the
BDLC’s attempt to transmit the byte loaded into the DLCBDR continually
loses arbitration, and the overall message length approaches the
12-byte limit as defined in SAE J1850.
If it becomes necessary to halt the IFR transmission attempts, the user
simply sets the TEOD bit in BCR2. If the BDLC is between transmission
attempts, it will make one more attempt to transmit the IFR byte. If it is
transmitting the byte when TEOD is set, the BDLC will continue the
transmission until it is successful or it loses arbitration to another
transmitter. At this point it will then discard the byte and make no more
transmit attempts.
NOTE:
When transmitting a Type 2 IFR, the user should monitor the number of
IFR bytes received to ensure that the overall message length does not
exceed the 12-byte limit for the length of SAE J1850 messages. The
user should set the TEOD bit when the 11th byte is received, which will
prevent the 12-byte limit from being exceeded.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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