Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Transmitting a
Type 1 IFR
To transmit a Type 1 IFR, the user loads the byte to be transmitted into
the DLCBDR and sets both the TSIFR bit and the TEOD bit. This will
direct the BDLC to attempt transmitting the byte written to the DLCBDR
one time, preceded by the appropriate Normalization Bit. If the
transmission is not successful, the byte will be discarded and no further
transmission attempts will be made. For an illustration of the steps
described below, refer to Transmitting A Type 1 IFR.
Step 1: Load the
IFR Byte into the
BDR
The user begins initiation of a Type 1 IFR by loading the desired IFR byte
into the DLCBDR. If a byte has already been written into the DLCBDR
for transmission as a new message, the user can simply write the IFR
byte to the DLCBDR, replacing the previously written byte. This must be
done before the first EOD symbol is received.
Step 2: Set the
TSIFR and TEOD Bits
The final step in transmitting a Type 1 IFR with the BDLC is to set the
TSIFR and TEOD bits in DLCBCR2. Setting both bits will direct the
BDLC to make one attempt at transmitting the byte in the DLCBDR as
an IFR. If the byte is transmitted successfully, or if an error or loss of
arbitration occurs, TEOD and TSIFR will be cleared and no further
transmit attempts will be made.
Transmitting a
Type 2 IFR
To transmit a Type 2 IFR, the user loads the byte to be transmitted into
the DLCBDR and sets the TSIFR bit. Once this is done, the BDLC will
attempt to transmit the byte in the DLCBDR as a single byte IFR,
preceded by the appropriate Normalization Bit. If the first BDLC loses
arbitration on the first attempt, it will make repeated attempts to transmit
this byte until it is successful, an error occurs or the user sets the TEOD
bit.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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