Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link Controller Module
Transmitting An In-Frame Response (IFR)
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
timely manner. If a loss of arbitration occurs while the Type 3 IFR is
being transmitted, transmission will halt immediately and the loss of
arbitration will be indicated in the DLCBSVR.
Transmit Multi-Byte
IFR 0
The Transmit Multi-Byte IFR 0 (TMIFR0) bit is used to transmit an SAE
J1850 Type 3 IFR without a CRC byte appended. If this bit is set after
the user has loaded the first byte of a multi-byte IFR into the DLCBDR,
the BDLC will begin transmitting that byte, preceded by the appropriate
Normalization Bit, onto the SAE J1850 bus. Once this happens a TDRE
interrupt will occur, indicating to the user that the next IFR byte should
be loaded into the DLCBDR. When the last byte to be transmitted is
written to the DLCBDR, the user sets the TEOD bit. This will cause an
EOD symbol to be transmitted following the last IFR byte.
As with the TSIFR and TMIFR1 bits, the TMIFR0 bit must be set before
the EOD symbol is received, or it will remain cleared and no IFR transmit
attempt will be made. The TMIFR0 bit will be cleared once the CRC byte
and EOD are transmitted, if an error is detected on the bus, if a loss of
arbitration occurs during the IFR transmission or if a transmitter
underrun occurs when the user fails to service the TDRE interrupt in a
timely manner. If a loss of arbitration occurs while the Type 3 IFR is
being transmitted, transmission will halt immediately and the loss of
arbitration will be indicated in the DLCBSVR.
NOTE:
The TMIFR0 bit should not be used to transmit a Type 1 IFR. If a loss of
arbitration occurs on the last bit of a byte being transmitted using the
TMIFR0 bit, two extra logic ones will be transmitted to ensure that the
IFR will not end on a byte boundary. This can cause an error in a Type
1 IFR.
Transmitting An IFR
with the BDLC
While the design of the BDLC makes the transmission of each type of
IFR similar, the steps necessary for sending each will be discussed.
Again, a discussion of the bytes making up any particular IFR is not
within the scope of this document. For a more detailed description of the
use of IFRs on an SAE J1850 network, refer to the SAE J1850
document.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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