Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Transmit Single
Byte IFR
The Transmit Single Byte IFR (TSIFR) bit in DLCBCR2 is used to
transmit Type 1 and Type 2 IFRs onto the SAE J1850 bus. If this bit is
set after a byte is loaded into the BDR, the BDLC will attempt to send
that byte, preceded by the appropriate Normalization Bit, as a single byte
IFR without a CRC. If arbitration is lost, the BDLC will automatically
attempt to transmit the byte again (without a Normalization Bit) as soon
as the byte winning arbitration completes transmission. Attempts to
transmit the byte will continue until either the byte is successfully
transmitted, the TEOD bit is set by the user or an error is detected on the
bus.
The user must set the TSIFR bit before the EOD following the main part
of the message frame is received, or no IFR transmit attempts will be
made for the current message. If another node does transmit an IFR to
this message or a reception error occurs, the TSIFR bit will be cleared.
If not, the IFR will be transmitted after the EOD of the next received
message.
The TSIFR bit will be automatically cleared once the EOD following one
or more IFR bytes has been received or an error is detected on the bus.
Transmit Multi-Byte
IFR 1
The Transmit Multi-Byte IFR 1 (TMIFR1) bit is used to transmit an SAE
J1850 Type 3 IFR with a CRC byte appended. If this bit is set after the
user has loaded the first byte of a multi-byte IFR into the DLCBDR, the
BDLC will begin transmitting that byte, preceded by the appropriate
Normalization Bit, onto the SAE J1850 bus. Once this happens a TDRE
interrupt will occur, indicating to the user that the next IFR byte should
be loaded into the DLCBDR. When the last byte to be transmitted is
written to the DLCBDR, the user sets the TEOD bit. This will cause a
CRC byte and an EOD symbol to be transmitted following the last IFR
byte.
As with the TSIFR bit, the TMIFR1 bit must be set before the EOD
symbol is received, or it will remain cleared and no IFR transmit attempt
will be made. The TMIFR1 bit will be cleared once the CRC byte and
EOD are transmitted, if an error is detected on the bus, if a loss of
arbitration occurs during the IFR transmission or if a transmitter
underrun occurs when the user fails to service the TDRE interrupt in a
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Freescale Semiconductor, Inc.
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