Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Once the EOF state is reflected in the DLCBSVR, this indicates to the
user that the message is complete, and that when another byte is
received it is the first byte of a new message.
Filtering Received
Messages
No message filtering hardware is included on the BDLC, so all message
filtering functions must be performed in software. Because the BDLC
handles each message on a byte-by-byte basis, message filtering can
be done as each byte is received, rather than after the entire message
is complete. This enables the CPU to decide while a message is still in
progress whether or not that message is of any interest.
At any point during a message, if the CPU determines that the message
is of no interest the IMSG bit can be set. Setting the IMSG bit commands
the BDLC not to update the DLCBSVR until the next valid SOF is
received. This prevents the CPU from having to service the BDLC for
each byte of every message sent over the network.
Receiving
Exceptions
As with a message transmission, this basic message reception flow can
be interrupted if errors are detected by the BDLC. This can occur if an
incorrect CRC is detected or if an invalid or out of range symbol appears
on the SAE J1850 bus. A problem can also arise if the CPU fails to
service the DLCBDR in a timely manner during a message reception.
Receiver Overrun Once a message byte has been received, the CPU must service the
DLCBDR before the next byte is received, or the first byte will be lost. If
the DLCBDR is not serviced quickly enough, the next byte received will
be written over the previous byte in the DLCBDR. No receiver overrun
indication is made to the CPU. If the CPU fails to service the BDLC
during the reception of an entire message, the byte remaining in the
DLCBDR will be last byte received (usually a CRC byte).
Once a receiver overrun occurs, there is no way for the CPU to recover
the lost byte(s), so the entire message should be discarded. To prevent
receiver overrun, the user should ensure that a BDLC RDRF interrupt
will be serviced before the next byte can be received. When polling the
DLCBSVR, the user should select a polling interval which will provide
timely monitoring of the BDLC.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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