Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link Controller Module
Receiving A Message
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Receiving a
Message with the
BDLC
Receiving a message using the BDLC is extremely straight-forward. As
each byte of a message is received and placed into the DLCBDR, the
BDLC will indicate this to the CPU with an Rx Data Register Full (RDRF)
status in the DLCBSVR. When an EOF symbol is received, indicating to
the CPU that the message is complete, this too will be reflected in the
DLCBSVR.
Outlined below are the basic steps to be followed for receiving a
message from the SAE J1850 bus with the BDLC. For an illustration of
this sequence, refer to Basic BDLC Receive Flowchart.
Step 1: When RDRF
Interrupt Occurs,
Retrieve Data Byte
When the first byte of a message following a valid SOF symbol is
received that byte is placed in the DLCBDR, and an RDRF state is
reflected in the DLCBSVR. No indication of the SOF reception is made,
since the end of the previous message is marked by an EOF indication.
The first RDRF state following this EOF indication should allow the user
to determine when a new message begins.
The RDRF interrupt is cleared when the received byte is read from the
DLCBDR. Once this is done, no further CPU intervention is necessary
until the next byte is received, and this step is repeated.
All bytes of the message, including the CRC byte, will be placed into the
DLCBDR as they are received for the CPU to retrieve.
Step 2: When an
EOF is Received,
the Message is
Complete
Once all bytes (including the CRC byte) have been received from the
bus, the bus will be idle for a time period equal to an EOD symbol. Once
the EOD symbol is received, the BDLC will verify that the CRC byte is
correct. If the CRC byte is not correct, this will be reflected in the
DLCBSVR.
If no In-Frame Response bytes are transmitted following the EOD
symbol, the EOD will transition into an EOF symbol. When the EOF is
received it will be reflected in the DLCBSVR, indicating to the user that
the message is complete. If IFR bytes do follow the first EOD symbol,
once they are complete another EOD will be transmitted, followed by an
EOF.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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