Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Receiving A Message
The design of the BDLC makes it especially easy to use for receiving
messages off of the SAE J1850 bus. When the first byte of a message
comes in, the DLCBSVR will indicate to the CPU that a byte has been
received. As each successive byte is received, that will in turn be
reflected in the DLCBSVR. When the message is complete and the EOF
has been detected on the bus, the DLCBSVR will reflect this, indicating
that the message is complete.
The basic steps required for receiving a message from the SAE J1850
bus are outlined below. For more information on receiving IFR bytes,
refer to Receiving An In-Frame Response (IFR).
BDLC Reception
Control Bits
The only control bit which is used for message reception, the IMSG bit,
is actually used to prevent message reception. As described in IMSG —
Ignore Message (Bit 7), when the IMSG bit is set BDLC interrupts of the
CPU are inhibited until the next SOF symbol is received. This allows the
BDLC to ignore the remainder of a message once the CPU has
determined that it is of no interest. This helps reduce the amount of CPU
overhead used to service messages received from the SAE J1850
network, since otherwise the BDLC would require attention from the
CPU for each byte broadcast on the network. The IMSG bit is cleared
when the BDLC receives an SOF symbol, or it can also be cleared by
the CPU.
NOTE: While the IMSG bit can be used to prevent the CPU from having to
service the BDLC for every byte transmitted on the SAE J1850 bus, the
IMSG bit should never be used to ignore the BDLC’s own
transmission. Because setting the IMSG bit prevents all DLCBSVR bits
from being updated until an SOF is received, the user would not receive
any further transmit-related interrupts until another SOF was received,
making it very difficult for the CPU to complete the transmission
correctly.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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