Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
error which will be indicated in the DLCBSVR. As with the other errors,
it is up to the user’s software to determine if another transmission
attempt should be made.
In-Frame
Response to a
Transmitted
Message
If an In-Frame Response (IFR) is received following the transmission of
a message, the status indicating that an IFR byte has been received will
be indicated in the DLCBSVR before an EOF is indicated. Refer to
Receiving An In-Frame Response (IFR) for a description of how to
handle the reception of IFR bytes.
Aborting a
Transmission
The BDLC module does not have a mechanism designed specifically for
aborting a transmission. Since the module transmits each message on
a byte-by-byte basis, there is little need to implement an abort
mechanism. If the user has loaded a byte into the DLCBDR to initiate a
message transmission and decides to send a different message, the
byte in the DLCBDR can be replaced, right up to the point that the
message transmission begins.
If the user has loaded a byte into the DLCBDR and then decides not to
send any message at all, the user can let the byte transmit, and when
the TDRE interrupt occurs let the transmitter underrun. This will cause
two extra logic ones followed by an EOF to be transmitted. While this
method may require a small amount of bus bandwidth, the need to do
this should be very rare. Replacing the byte originally written to the BDR
with $FF will also increase the probability of the transmitter losing
arbitration if another node begins transmitting at the same time, also
reducing the bus bandwidth needed.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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