Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Step 7- Clear
Pending BDLC
Interrupts
In order to ensure that the BDLC does not immediately generate a CPU
interrupt when interrupts are enabled, the user should read the
DLCBSVR to determine if any BDLC interrupt sources are pending
before setting the IE bit in the BCR1. If the BSVR reads as a%00000000,
no interrupts are pending and the user is free to enable BDLC interrupts,
if desired.
If the DLCBSVR indicates that an interrupt is pending, the user should
perform whatever actions are necessary to clear the interrupt source
before enabling the interrupts. Whether any interrupts are pending will
depend primarily upon how much time passes between the exit from
loopback modes and enabling the BDLC and the enabling of interrupts.
It is a good practice to always clear any source of interrupts before
enabling interrupts on any MCU subsystem.
If any interrupts are pending (DLCBSVR ≠ %00000000), then each
interrupt source should be dealt with accordingly. Once all of the
interrupt sources have been dealt with, the DLCBSVR should
read%00000000, and the user is then free to enable BDLC interrupts.
Step 8- Enable
BDLC Interrupts
The last step in initializing the BDLC module is to enable interrupts to the
CPU, if so desired. This is done by simply setting the IE bit in the
DLCBCR1. Following this, the BDLC module is ready for operating in
interrupt mode. If the user chooses not to enable interrupts, the
DLCBSVR must be polled periodically to ensure that state changes in
the BDLC are detected and dealt with appropriately.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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