Datasheet

Byte Data Link Controller Module
Reset Initialization/Basic Operation
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Step 4- Initialize
DLCBCR1
The next step in BDLC initialization is to write the configuration bits in
DLCBCR1. The CLKS bit should be written to its desired values at this
time, following which it will become read-only. The IE bit should be
written as a logic zero at this time so BDLC interrupts of the CPU will
remain masked for the time being. The IMSG bit should be written as a
logic one to prevent any receive events from setting the DLCBSVR until
a valid SOF (or BREAK) symbol has been received by the BDLC.
Exiting Loopback
Mode and
Enabling the BDLC
Once the configuration bits have been written to the desired values, the
BDLC should be taken out of loopback and connected to the SAE J1850
bus. This is done by clearing the DLOOP bit and then setting the BDLCE
bit in the DLCSCR.
Step 5- Perform
Loopback Tests
(optional)
Once the BDLC is configured for desired operation, the user may wish
to perform digital and/or analog loopback tests to determine the integrity
of the link to the SAE J1850 network. This would involve leaving the
DLOOP bit (DLCBCR2) set, setting the BDLCE bit, preforming the
desired loopback tests and finally exiting digital loopback mode by
clearing DLOOP in the DLCBCR2.
Step 6- Exit
Loopback Mode
and enable the
BDLC
If loopback mode tests are not to be preformed the BDLC can be
removed from digital loopback mode by clearing the DLOOP bit. The
BDLC can then be enabled by setting the BDLCE bit in the DLCSCR.
Once DLOOP is cleared and BDLCE is set, the BDLC is ready for SAE
J1850 communication. However, to ensure that the BDLC does not
attempt to receive a message already in progress or to transmit a
message while another device is transmitting, the BDLC must first
observe an EOF symbol on the bus before the receiver will be activated.
To activate the transmitter, the BDLC will need to observe an
Inter-Frame Separator symbol.
Enabling BDLC
Interrupts
The final step in readying the BDLC for proper communication is to clear
any pending interrupt sources and then, if desired, enable BDLC
interrupts of the CPU.
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Freescale Semiconductor, Inc.
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