Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
entail change of state indications in the DLCBSVR which must be dealt
with. Once this is complete, CPU interrupts can be enabled (if desired),
and then the BDLC module is capable of SAE J1850 serial network
communication. For an illustration of the sequence necessary for
initializing the BDLC, refer to Figure 128.
Initializing the
Configuration Bits
The first step necessary for initializing the BDLC following an MCU reset
is to write the desired values to each of the BDLC control registers. This
is best done by storing predetermined initialization values directly into
these registers. The following description outlines a basic flow for
initializing the BDLC. This basic flow does not detail more elaborate
initialization routines, such as performing digital and analog loopback
tests before enabling the BDLC for SAE J1850 communication.
However, from the following descriptions and the BDLC specification,
the user should be able to develop routines for performing various
diagnostic procedures such as loopback tests.
Step 1 - Initialize
DLCBARD
Begin initialization of the configuration bits by writing the desired analog
transceiver configuration data into the DLCBARD register. Following this
write to DLCBARD, all of these bits will become read only.
Step 2- Initialize
DLCBRSR
The next step in BDLC initialization is to write the desired bus clock
divisor minus one into the DLCBRSR register. The divisor should be
chosen to generate a 1 MHz or 1.048576 MHz mux interface clock
( f
bdlc
).
Following this write to DLCBRSR, all of these bits will become read only.
Step 3- Initialize
DLCBCR2
The next step in BDLC initialization should be writing the configuration
bits into the DLCBCR2 register. This initialization description assumes
that the BDLC will be put into normal mode (not 4X mode), and that the
BDLC should not yet exit either digital or analog loopback mode.
Therefore, this step should write SMRST and DLOOP as logic ones,
RX4XE as a logic zero, write NBFS to the desired level, and write TEOD,
TSIFR, TMIFR1 and TMIFR0 as logic zeros. These last four bits MUST
be written as logic zeros in order to prevent undesired operation of the
BDLC.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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