Datasheet

Byte Data Link Controller Module
External Pin Descriptions
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Register functionality is modified in special test mode.
IDLE Idle (Bit 0)
This bit indicates when the BDLC is idle.
1 = BDLC has received IFS and no data is being transmitted or
received.
0 = BDLC is either transmitting or receiving data.
NOTE: BDLC is only idle after receiving IFS. The IDLE bit is 0 during reset since
the BDLC needs to wait for an IFS before becoming idle. Noise on the
bus will be filtered and the IDLE bit will remain unchanged.
External Pin Descriptions
The BDLC module has a control bit, BDLCE, for two external pins, PM0
and PM1. The BDLCE bit enables and disables the BDLC and its J1850
functions. The transmit pin (Txp) function is multiplexed on the PM1 port
and the receive pin (Rxp) function is multiplexed on the PM0 port. The
BDLC pins are shared with the CAN0 pins. When the BDLC is enabled,
the BDLC function takes control of these two shared pins.
NOTE: If both BDLC and CAN0 are enabled, the CAN0 will take control of these
two pins and no BDLC function will occur on these pins.
Reset Initialization/Basic Operation
The reset state of each individual bit is listed within the Register
Descriptions section Register Descriptions which details the registers
and their bit-fields.
This section includes sample flows for initializing the BDLC and using it
to transmit and receive messages.
Initialization
Sequence
To initialize the BDLC, the user should first write the desired data to the
configuration bits. The BDLC should then be taken out of digital and
analog loopback mode and enabled. Exiting from loopback mode will
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...