Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
BDLC Control
Register (DLCSCR)
The following register enables the BLDC_IP.
READ: any time
WRITE: any time
BDLCE
— BDLC Enable (Bit 4)
This bit serves as a mux interface clock (f
bdlc
) enable/disable for
power savings.
1 = The mux interface clock (f
bdlc
) and BDLC are enabled to allow
J1850 communications to take place.
0 = The mux interface clock (f
bdlc
) is disabled shutting down the
BDLC for power saving. Bus clocks are still running allowing
registers to be accessed.
BDLC Status
Register
(DLCBSTAT)
This register indicates the status of the BDLC.
READ: any time
WRITE: ignored in normal and emulation modes
Address Offset: $0006
Bit 7 654321Bit 0
Read: 0 0 0
BDLCE
0 0 0 0
Write:
Reset: 00000000
= Unimplemented
Address Offset: $0007
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0 0 IDLE
Write: Unimplemented Reserved Unimplemented
Reset: 00000000
= Reserved or Unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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