Datasheet

Byte Data Link Controller Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
NOTE: The BRSR is always loaded with “desired divisor” -1 and comes out of
reset programmed for a divide by 1 clock rate (BRSR = $00).
Table 118 BDLC Rate Selection for Binary Frequencies
IP bus clock frequency R[5:0] division
f
bdlc
f
CLOCK
=1.048576 MHz $00 1 1.048576 MHz
f
CLOCK
=2.09715 MHz $01 2 1.048576 MHz
f
CLOCK
=3.14573 MHz $02 3 1.048576 MHz
f
CLOCK
=4.19430 MHz $03 4 1.048576 MHz
f
CLOCK
=8.38861 MHz $07 8 1.048576 MHz
f
CLOCK
=10.48576 MHz $09 10 1.048576 MHz
f
CLOCK
=67.10886 MHz $3F 64 1.048576 MHz
Table 119 BDLC Rate Selection for Integer Frequencies
IP bus clock frequency R[5:0] division
f
bdlc
f
CLOCK
=1.00000 MHz $00 1 1.000000 MHz
f
CLOCK
=2.00000 MHz $01 2 1.000000 MHz
f
CLOCK
=3.00000 MHz $02 3 1.000000 MHz
f
CLOCK
=4.00000 MHz $03 4 1.000000 MHz
f
CLOCK
=8.00000 MHz $07 8 1.000000 MHz
f
CLOCK
=10.00000 MHz $09 10 1.000000 MHz
f
CLOCK
=64.00000 MHz $3F 64 1.000000 MHz
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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