Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
BDLC Rate Select
Register (DLCBRSR)
This register determines the divider prescaler value for the mux interface
clock (f
bdlc
).
READ: any time
WRITE: write once in normal and emulation modes.
Register functionality modified in special test mode.
Writes to unimplemented bits 7, 6 are ignored.
R5-R0
— Rate Select (Bits 5-0)
These bits determine the amount by which the frequency of the
system clock signal is divided to generate the MUX Interface clock
(f
bdlc
) which defines the basic timing resolution of the MUX Interface.
The value programmed into these bits is dependent on the chosen
system clock frequency. See Table 118 and Table 119 for example
rate selects for different bus frequencies. All divisor values from divide
by 1 to divide by 64 are possible, but are not shown in the tables.
NOTE: Although the maximum divider is 64, a divider which will generate a 1
MHz or 1.048576 MHz
f
bdlc
must be selected in order for J1850
communications to occur.
Address Offset: $0005
Bit 7 654321Bit 0
Read: 0 0
R5 R4 R3 R2 R1 R0
Write: Unimplemented
Reset: 00000000
= Unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...