Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
BDLC Analog
Round Trip Delay
Register
(DLCBARD)
This register is used to program the BDLC so that it compensates for the
round trip delays of different external transceivers. Also the polarity of
the receive pin (RxP) is set in this register.
READ: any time
WRITE: write once in normal and emulation modes.
Register functionality modified in special test mode.
Writes to unimplemented bits 7, 5, 4 are ignored.
RXPOL
— Receive Pin Polarity (Bit 6)
The Receive pin Polarity bit is used to select the polarity of incoming
signal on the receive pin. Some external analog transceiver inverts
the receive signal from the J1850 bus before feeding back to the
digital receive pin.
1 = Select normal/true polarity; true non-inverted signal from J1850
bus, i.e., the external transceiver does not invert the receive
signal.
0 = Select inverted polarity, where external transceiver inverts the
receive signal.
BO3-BO0
— BDLC Analog Roundtrip Delay Offset Field (Bits 3-0)
BO[3:0] adjust the transmitted symbol timings to account for the
differing roundtrip delays found in different SAE J1850 analog
transceivers. The allowable delay range is from 9
µs to 24 µs, with a
nominal target of 16
µs (reset value). Refer to Table 117 for the
BO[3:0] values corresponding to the expected transceiver delays and
the resultant transmitter timing adjustment (in mux interface clock
periods (t
bdlc
)). Refer to the analog transceiver device specification for
Address Offset: $0004
Bit 7 654321Bit 0
Read: 0
RXPOL
00
BO3 BO2 BO1 BO0
Write:
Reset: 01000111
= Unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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