Datasheet

Byte Data Link Controller Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
If the user writes the first byte of a message to be transmitted to the
DLCBDR and then determines that a different message should be
transmitted, the user can write a new byte to the DLCBDR up until the
transmission begins.This new byte will replace the original byte in the
DLCBDR.
From the time a byte is written to the DLCBDR until it is transferred to
the transmit shift register, the transmit shadow register is considered
full and the byte pending transmission. If one of the IFR transmission
control bits (TSIFR, TMIFR1, or TMIFR0 in DLCBCR2) is also set, the
byte is pending transmission as an IFR. A byte pending transmission
will be flushed from the transmit shadow register and the transmission
canceled if one of the following occurs: a loss of arbitration or
transmitter error on the byte currently being transmitted; a symbol
error, framing error, bus fault, or BREAK symbol is received. If the
byte pending transmission is an IFR byte, the reception of a message
with a CRC error will also cause the byte in the transmit shadow
register to be flushed.
To abort an in-progress transmission, the programmer should simply
stop loading more data into the BDR. This will cause a transmitter
underrun error and the BDLC will automatically disable the transmitter
on the next non-byte boundary. This means that the earliest a
transmission can be halted is after at least one byte (plus two extra
1-bits) has been transmitted. The receiver will pick this up as an error
and relay it in the State Vector Register as an invalid symbol error.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...