Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
BDLC Data
Register (DLCBDR)
This register is used to pass the data to be transmitted to the J1850 bus
from the CPU to the BDLC. It is also used to pass data received from the
J1850 bus to the CPU.
READ: any time
WRITE: any time
D7:D0
— Receive/Transmit Data (Bits 7 - 0)
Each data byte (after the first one) should be written only after a “Tx
Data Register Empty” (TDRE) interrupt has occurred, or the
DLCBSVR register has been polled indicating this condition.
Data read from this register will be the last data byte received from the
J1850 bus. This received data should only be read after a “Rx Data
Register Full” (RDRF) or “Received IFR byte” (RXIFR) interrupt has
occurred or the DLCBSVR register has been polled indicating either
of these two conditions.
The DLCBDR register is double buffered via a transmit shadow
register and a receive shadow register. After the byte in the transmit
shift register has been transmitted, the byte currently stored in the
transmit shadow register is loaded into the transmit shift register.
Once the transmit shift register has shifted the first bit out, the TDRE
flag is set, and the shadow register is ready to accept the next byte of
data.
The receive shadow register works similarly. Once a complete byte
has been received, the receive shift register stores the newly received
byte into the receive shadow register. The RDRF flag (or RXIFR flag
if the received byte is part of an IFR) is set to indicate that a new byte
of data has been received. The programmer has one BDLC byte
reception time to read the shadow register and clear the RDRF or
RXIFR flag before the shadow register is overwritten by the newly
received byte.
Address Offset: $0003
Bit 7 654321Bit 0
Read:
D7 D6 D5 D4 D3 D2 D1 D0
Write:
Reset: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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