Datasheet

Byte Data Link Controller Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
However, if the programmer wishes to transmit a single byte, the
programmer should load the byte into the DLCBDR and then set the
TMIFR0 bit before the EOD symbol has been received. Once the
TDRE flag is set and interrupt occurs (if enabled), the programmer
should then set the TEOD bit in DLCBCR2. This will result in the byte
in the DLCBDR being the only byte transmitted.
The user must set the TMIFR0 bit before the EOF following the main
part of the message frame is received, or no IFR transmit attempts will
be made for the current message. If another node transmits an IFR to
this message, the user must set the TMIFR0 bit before the
normalization bit is received or no IFR transmit attempts will be made
for the message. If another node does transmit a successful IFR or a
reception error occurs, the TMIFR0 bit will be cleared. If not, the IFR
will be transmitted after the EOD of the next received message.
If a transmitter underrun error occurs during transmission (caused by
the programmer not writing another byte to the DLCBDR following the
TDRE flag being set) the BDLC will automatically disable the
transmitter after the byte currently in the shifter plus two extra 1-bits
have been transmitted. The receiver will pick this up as an framing
error and relay it in the State Vector Register as an invalid symbol
error. The TMIFR0 bit will also be cleared.
If a loss of arbitration occurs when the BDLC is transmitting a multiple
byte IFR without CRC, the BDLC will go to the loss of arbitration state,
set the appropriate flag and cease transmission. The TMIFR0 bit will
be cleared and no attempt will be made to retransmit the byte in the
DLCBDR. If loss of arbitration occurs in the last bit of the IFR byte, two
additional one bits (a passive long followed by an active short) will be
sent out.
NOTE: The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
on the J1850 bus from corrupting a message.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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