Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
If a loss of arbitration occurs when the BDLC is transmitting a multiple
byte IFR with CRC, the BDLC will go to the loss of arbitration state,
set the appropriate flag and cease transmission. The TMIFR1 bit will
be cleared and no attempt will be made to retransmit the byte in the
DLCBDR. If loss of arbitration occurs in the last bit of the IFR byte, two
additional one bits (a passive long followed by an active short) will be
sent out.
NOTE: The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
on the J1850 bus from corrupting a message.
TMIFR0 — Transmit Multiple Byte IFR with no CRC (Type 3)
This bit is used to request the BDLC to transmit the byte in the BDLC
Data Register (DLCBDR) as the first byte of a multiple byte IFR
without CRC. Response IFR bytes are still subject to J1850 message
length maximums.
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received the BDLC will
attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last
IFR byte has been written into DLCBDR register. After TEOD
has been set, the last IFR byte to be transmitted will be the last
byte which was written into the DLCBDR register.
0 = The TMIFR0 bit will be automatically cleared once the BDLC
has successfully transmitted the EOD symbol, by the detection
of an error on the multiplex bus, a transmitter underrun, or loss
of arbitration.
After the byte in the DLCBDR has been loaded into the transmit shift
register, the TDRE flag will be set in the DLCBSVR register, similar to
the main message transmit sequence. If the interrupt enable bit (IE in
DLCBCR1) is set, an interrupt request from the BDLC is generated.
The programmer should then load the next byte of the IFR into the
DLCBDR for transmission. When the last byte of the IFR has been
loaded into the DLCBDR, the programmer should set the TEOD bit in
the DLCBCR2 register. This will instruct the BDLC to transmit an EOD
symbol, indicating the end of the IFR portion of the message frame.
The BDLC will not append a CRC.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...