Datasheet

Byte Data Link Controller Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
0 = The TMIFR1 bit will be automatically cleared once the BDLC
has successfully transmitted the CRC byte and EOD symbol,
by the detection of an error on the multiplex bus, a transmitter
underrun, or loss of arbitration.
After the byte in the DLCBDR has been loaded into the transmit shift
register, the TDRE flag will be set in the DLCBSVR register, similar to
the main message transmit sequence. If the interrupt enable bit (IE in
DLCBCR1) is set, an interrupt request from the BDLC is
generated.The programmer should then load the next byte of the IFR
into the DLCBDR for transmission. When the last byte of the IFR has
been loaded into the DLCBDR, the programmer should set the TEOD
bit in the BDLC control register 2 (DLCBCR2). This will instruct the
BDLC to transmit a CRC byte once the byte in the DLCBDR is
transmitted, and then transmit an EOD symbol, indicating the end of
the IFR portion of the message frame.
However, if the programmer wishes to transmit a single byte followed
by a CRC byte, the programmer should load the byte into the
DLCBDR and then set the TMIFR1 bit before the EOD symbol has
been received. Once the TDRE flag is set and interrupt occurs (if
enabled), the programmer should then set the TEOD bit in DLCBCR2.
This will result in the byte in the DLCBDR being the only byte
transmitted before the IFR CRC byte.
The user must set the TMIFR1 bit before the EOF following the main
part of the message frame is received, or no IFR transmit attempts will
be made for the current message. If another node transmits an IFR to
this message, the user must set the TMIFR1 bit before the
normalization bit is received or no IFR transmit attempts will be made
for the message. If another node does transmit a successful IFR or a
reception error occurs, the TMIFR1 bit will be cleared. If not, the IFR
will be transmitted after the EOD of the next received message.
If a transmitter underrun error occurs during transmission (caused by
the programmer not writing another byte to the DLCBDR following the
TDRE flag being set) the BDLC will automatically disable the
transmitter after the byte currently in the shifter plus two extra 1-bits
have been transmitted. The receiver will pick this up as an framing
error and relay it in the State Vector Register as an invalid symbol
error. The TMIFR1 bit will also be cleared.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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