Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
0 = The TSIFR bit will be automatically cleared once the EOD
following one or more IFR bytes has been received or an error
is detected on the bus.
The user must set the TSIFR bit before the EOF following the main
part of the message frame is received, or no IFR transmit attempts will
be made for the current message. If another node transmits an IFR to
this message, the user must set the TSIFR bit before the
normalization bit is received or no IFR transmit attempts will be made
for the message. If another node does transmit a successful IFR or a
reception error occurs, the TSIFR bit will be cleared. If not, the IFR will
be transmitted after the EOD of the next received message.
If a loss of arbitration occurs when the BDLC attempts transmission,
after the IFR byte winning arbitration completes transmission, the
BDLC will again attempt to transmit the byte in the DLCBDR (with no
normalization bit). The BDLC will continue transmission attempts until
an error is detected on the bus, or TEOD is set by the CPU, or the
BDLC transmission is successful.
NOTE:
Setting the TEOD bit before transmission of the IFR byte will direct the
BDLC to make only one attempt at transmitting the byte.
If loss of arbitration occurs in the last bit of the IFR byte, two additional
‘1’ bits will not be sent out because the BDLC will attempt to
retransmit the byte in the transmit shift register after the IFR byte
winning arbitration completes transmission.
TMIFR1
— Transmit Multiple Byte IFR with CRC (Type 3)
This bit requests the BDLC to transmit the byte in the BDLC Data
Register (DLCBDR) as the first byte of a multiple byte IFR with CRC
or as a single byte IFR with CRC.Response IFR bytes are still subject
to J1850 message length maximums.
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received the BDLC will
attempt to transmit the appropriate normalization bit followed
by IFR bytes.The programmer should set TEOD after the last
IFR byte has been written into DLCBDR register. After TEOD
has been set and the last IFR byte has been transmitted, the
CRC byte is transmitted.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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