Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Shadow Register have been transmitted. Once TEOD is set, the
transmit data register empty flag (TDRE) in the BDLC State Vector
Register (DLCBSVR) is cleared to allow lower priority interrupts to
occur. This bit is also used to end an IFR. Bits TSIFR, TMIFR1, and
TMIFR0 determine whether a CRC byte is appended before EOD
transmission for IFRs.
1 = Transmit EOD symbol.
0 = The TEOD bit will be automatically cleared after the first CRC
bit is sent, or if an error or loss of arbitration is detected on the
bus. When TEOD is used to end an IFR transmission, TEOD
is cleared when the BDLC receives back a valid EOD symbol,
or an error condition or loss of arbitration occurs.
TSIFR, TMIFR1, TMIFR0
— Transmit In-Frame Response Control (Bits
2-0)
These three bits control the type of In-Frame Response being sent. The
programmer should not set more than one of these control bits to a one
at any given time. However, if more than one of these three control bits
are set to one, the priority encoding logic will force the internal register
bits to a known value as shown in the following table. But, when these
bits are read, they will be the same as written earlier. For instance, if
“011” is written to TSIFR, TMIFR1, TMIFR0, then internally, they’ll be
encoded as “010”. However, when these bits are later read back, it’ll still
be “011”.
Table 116 Transmit In-Frame Response Control Bit Priority
Encoding
Write Read Actual (internal register)
TSIFR TMIFR1 TMIFR0 TSIFR TMIFR1 TMIFR0 TSIFR TMIFR1 TMIFR0
000000000
1XX1XX100
01X01X010
001001001
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...