Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

System ConÞguration
MC9S12DP256 — Revision 1.1
System Configuration
MCU Variabilities
Part ID Register
Assignments
The PARTID register is located in the IPBI (IP-Bus interface) at address
$__1A,$__1B. It contains a unique part ID for each revision of the chip.
Table 11 contains the assigned part ID numbers.
The coding is as follows:
Bit 15-12: Major Family identifier
Bit 11-8 : Minor Family identifier
Bit 7-4: Major mask revision number including FAB transfers
Bit 3-0: Minor - non full - mask set revisions
Table 11 Assigned Part ID Numbers
Part Number Mask Set Number PARTID
MC9S12DP256 0K36N
0001_0010,
0101_0110
MC9S12DP256 0K79X
0000_0000,
0001_0000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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