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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 80 (14x14) 16-Bit 25 MHz I/O number 59

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Table Of Contents

List of Sections
Table of Contents
General Description
- Contents
- Introduction
- Features
- MC9S12DP256 112-Pin Block Diagram
- Ordering Information
Central Processing Unit (CPU)
- Contents
- Introduction
- Programming Model
- Data Types
- Addressing Modes
- Indexed Addressing Modes
- Opcodes and Operands
- Instruction Set Summary
Pinout and Signal Description
- Contents
- MC9S12DP256 Pin Assignments in 112-pin QFP
- Power Supply Pins
- Signal Descriptions
- Port Signals
System Configuration
- Contents
- Introduction
- Modules Variabilities
- MCU Variabilities
Registers
- Contents
- Register Block
Operating Modes
- Contents
- Introduction
- Operating Modes
- Background Debug Mode
- Security
Resource Mapping
- Contents
- Introduction
- Internal Resource Mapping
- Flash EEPROM mapping through internal Memory Expansion
- Miscellaneous System Control Register
- Memory Maps
Bus Control and Input/Output
- Contents
- Introduction
- Detecting Access Type from External Signals
- Stretched Bus Cycles
- PIPE Status Signals
- Registers
Resets and Interrupts
- Contents
- Introduction
- Register Map
- Exception Priority
- Maskable interrupts
- Latching of Interrupts
- Register Descriptions
- Resets
- Effects of Reset
- Register Stacking
Voltage Regulator (VREG)
- Contents
- Overview
- Features
- Block Diagram
- Functional Description
- External Pin Connection
- Reset Initialization
- Modes of Operation
Flash EEPROM 256K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
EEPROM 4K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Interrupt Operation
Port Integration Module
- Contents
- Overview
- Block Diagram
- External Pin Descriptions
- 80 Pin QFP bond-out version
- Register Map
- Register Descriptions
- Reset Initialization
- Functional Description
- Low Power Options
- Interrupt Operation
Clocks and Reset Generator (CRG)
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Interrupt Operation
- Low Power Options
Pulse Width Modulator (PWM)
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Register Descriptions
- Functional Description
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
Enhanced Capture Timer (ECT)
- Contents
- Overview
- Features
- Modes of Operation
- Abbreviations
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Modes of Operation
- Interrupts
- Description of Interrupt Operation
Serial Communications Interface (SCI)
- Contents
- Overview
- Features
- Modes of Operation
- SCI Interface Diagram
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Modes of Operation
- Interrupt Operation
Serial Peripheral Interface (SPI)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Low Power Mode Options
- Errata
- Reset
- Interrupts
Inter-IC Bus (IIC)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- I-Bus Protocol
- Interrupt Operation
- Modes of Operation
- Programming
MSCAN
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Functional Description
- Register Descriptions
- Modes of Operation
- Low Power Options
- Interrupt Operation
Analog to Digital Converter
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Sample Conversion
- General Purpose Input Ports
Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
Background Debug Module (BDM)
- Contents
- Overview
- Interface Signals
- Registers
- Operation
- Modes of Operation
- Low-Power Options
- Interrupt Operation
Breakpoint (BKP) Module
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Descriptions
- Functional Description
- Breakpoint Operating Modes
- Breakpoint Types
- Modes of Operation
- Low Power Options
- Reset Initialization
- Interrupt Operation
- General Purpose I/O Ports
Revision History
- Changes from Rev 1.0 to Rev 1.1
Glossary
Literature Updates
- Literature Distribution Centers
- Customer Focus Center
- Microcontroller Division’s Web Site

Byte Data Link Controller Module

MC9S12DP256 — Revision 1.1

Byte Data Link Controller Module

RX4XE — Receive 4X Enable (Bit 5)

This bit determines if the BDLC operates at normal transmit and

receive speed (10.4 kbps) or receive only at 41.6 kbps. This feature

is useful for fast download of data into a J1850 node for diagnostic or

factory programming of the node.

1 = When set, the BDLC is put in 4X (41.6 kbps) receive only

operation.

0 = When cleared, the BDLC transmits and receives at 10.4 kbps.

Reception of a BREAK symbol automatically clears this bit and

sets the symbol invalid or out of range flag (DLCBSVR = $1C).

The effect of 4X receive operation on receive symbol timing boundaries

is described in section Transmit and Receive Symbol Timing

Specifications.The RX4XE bit is not affected by entry or exit from BDLC

stop or wait modes.

NBFS

— Normalization Bit Format Select (Bit 4)

This bit controls the format of the Normalization Bit (NB). SAE J1850

strongly encourages the use of an active long, ‘0’, for In-Frame

Responses containing CRC and active short, ‘1’, for In-Frame

Responses without CRC.

1 = NB that is received or transmitted is a ‘0’ when the response

part of an In-Frame Response (IFR) ends with a CRC byte. NB

that is received or transmitted is a ‘1’ when the response part

of an In-Frame Response (IFR) does not end with a CRC byte.

0 = NB that is received or transmitted is a ‘1’ when the response

part of an In-Frame Response (IFR) ends with a CRC byte. NB

that is received or transmitted is a ‘0’ when the response part

of an In-Frame Response (IFR) does not end with a CRC byte.

TEOD

— Transmit End of Data (Bit 3)

This bit is set by the programmer to indicate the end of a message

being sent by the BDLC. It will append an 8-bit CRC after completing

transmission of the current byte in the Tx Shift Register followed by

the EOD symbol. If the transmit shadow register (refer to Rx & Tx

Shadow Registers for a description of the transmit shadow register)

is full when TEOD is set, the CRC byte and EOD will be transmitted

after the current byte in the Tx Shift Register and the byte in the Tx

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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