Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
0 = Clearing SMRST after it has been set will cause the generation
of a state machine reset.After SMRST is cleared, the BDLC
requires the bus to be idle for a minimum of an End of Frame
symbol (EOF) time before allowing the reception of a
message. The BDLC requires the bus to be idle for a minimum
of an Inter-Frame Separator symbol (IFS) time before allowing
any message to be transmitted.
DLOOP
— Digital Loopback Mode (Bit 6)
This bit determines the source to which the input of the digital filter is
connected and can be used to isolate bus fault conditions. If a fault
condition has been detected on the bus, this control bit allows the
programmer to disconnect the digital filter from input from the receive
pin (RxP) and connect it to the transmit output to the pin (TxP). In this
configuration, data sent from the transmit buffer should be reflected
back into the receive buffer. If no faults exist in the digital block, the
fault is in the physical interface block or elsewhere on the J1850 bus.
1 = When set, digital filter input is connected to the transmitter
output. The BDLC is now in Digital Loopback Mode of
operation. The transmit pin (TxP) is driven low and not driven
by the transmitter output.
0 = When cleared, digital filter input is connected to receive pin
(RxP) and the transmitter output is connected to the transmit
pin (TxP). The BDLC is taken out of Digital Loopback Mode
and can now drive and receive from the J1850 bus normally.
After writing DLOOP to zero, the BDLC requires the bus to be
idle for a minimum of and End of Frame symbol time before
allowing a reception of a message. The BDLC requires the bus
to be idle for a minimum of an Inter-Frame Separator symbol
time before allowing any message to be transmitted.
NOTE:
The DLOOP bit is a fault condition aid and should never be altered after
the DLCBDR is loaded for transmission. Changing DLOOP during a
transmission may cause corrupted data to be transmitted onto the J1850
network.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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