Datasheet

Byte Data Link Controller Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
JMP SERVE8 Service condition #8
END
Note that the NOPs are just used to align the JMPs onto 4-byte
boundaries so that the value in the DLCBSVR may be used intact.
Each of the service routines must end with an ‘RTI’ instruction to
guarantee correct continued operation of the device. Note also that
the first entry can be omitted since it corresponds to no interrupt
occurring.
The service routines should clear all of the sources that are causing
the pending interrupts.Note that the clearing of a high priority interrupt
may still leave a lower priority interrupt pending, in which case bits I0,
I1 and I2 of the DLCBSVR will then reflect the source of the remaining
interrupt request.
If fewer states are used, or if a different software approach is taken,
the jump table may be made smaller or omitted altogether.
BDLC Control
Register 2
(DLCBCR2)
This register controls transmitter operations of the BDLC.
READ: any time
WRITE: any time
SMRST
— State Machine Reset (Bit 7)
The programmer can use this bit to reset the BDLC state machines to
an initial state after the user put the off-chip analog transceiver in loop
back mode.
1 = Setting SMRST arms the state machine reset generation
logic.Setting SMRST does not affect BDLC behavior in any
way.
Address Offset: $0002
Bit 7 654321Bit 0
Read:
SMRST DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0
Write:
Reset: 01000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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