Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Bits I0, I1, I2, and I3 are cleared by a read of the DLCBSVR register
except when the BDLC Data Register needs servicing (RDRF, RXIFR,
or TDRE conditions). RXIFR and RDRF can only be cleared by a read
of the BSVR register followed by a read of DLCBDR. TDRE can either
be cleared by a read of the DLCBSVR register followed by a write to the
DLCBDR register, or by setting the TEOD bit in BCR2. TDRE can also
be cleared by the setting of the Loss of Arbitration, CRC Error, or Invalid
Symbol flags.
Upon receiving a BDLC interrupt, the user may read the value within the
DLCBSVR, transferring it to the CPU’s Index Register. The value may
then be used to index into a ‘jump table’, with entries 4 bytes apart, to
quickly enter the appropriate service routine. For example:
SERVICELDX BSVR Fetch State Vector Number
JMP JMPTAB,X Enter service routine,
* (must end in an ‘RTI’)
*
JMPTAB JMP SERVE0 Service condition #0
NOP
JMP SERVE1 Service condition #1
NOP
JMP SERVE2 Service condition #2
NOP
... ... ...
Table 115 Interrupt Sources
BSVR I3 I2 I1 I0 Interrupt Source Priority
$00 0000 No Interrupts Pending 0 (lowest)
$04 0001 Received EOF 1
$08 0010 Received IFR byte (RXIFR) 2
$0C 0011Rx data register full (RDRF) 3
$10 0100Tx data register empty (TDRE) 4
$14 0101 Loss of arbitration 5
$18 0110 CRC error 6
$1C 0111Symbol invalid or out of range 7
$20 1000 Wakeup 8 (highest)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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