Datasheet

Byte Data Link Controller Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
If the programmer does not wish to use the interrupt capability of the
BDLC, the BDLC State Vector Register (DLCBSVR) can be polled
periodically by the programmer to determine BDLC states. Refer to
BDLC State Vector Register (DLCBSVR) for a description of DLCBSVR
register and how to clear interrupt requests.
WCM
— Wait Clock Mode (Bit 0)
This bit determines how the BDLC responds when the CPU enters
WAIT mode. As described in Modes of Operation, the BDLC can
respond by either entering BDLC_STOP mode, where all internal
clocks are stopped, or entering BDLC_WAIT mode where internal
clocks are allowed to run.
1 = Stop BDLC internal clocks during CPU wait mode
(BDLC_STOP)
0 = Run BDLC internal clocks during CPU wait mode
(BDLC_WAIT)
BDLC State Vector
Register
(DLCBSVR)
This register is provided to substantially decrease the CPU overhead
associated with servicing interrupts while under operation of a MUX
protocol. It provides a index offset that is directly related to the BDLC’s
current state, which can be used with a user supplied jump table to
rapidly enter an interrupt service routine. This eliminates the need for the
user to maintain a duplicate state machine in software.
READ: any time
WRITE: ignored
I[3:0]
— Interrupt State Vector (Bits 5–2)
These bits indicate the source of the interrupt request that is currently
pending. The encoding of these bits follows
Address Offset: $0001
Bit 7 654321Bit 0
Read: 0 0 I3 I2 I1 I0 0 0
Write:
Reset: 00000000
= Unimplemented
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