Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
0 = Enable DLCBSVR Updates. This bit is automatically cleared by
the reception of a SOF symbol or a BREAK symbol. It will then
allow updates of the state vector register to occur.
There are two situations in which interrupts will not be masked by the
IMSG bit: when a wakeup interrupt occurs; and when a receiver error
occurs which causes a byte pending transmission to be flushed from the
transmit shadow register. See BDLC Data Register (DLCBDR) for a
description of the conditions which cause a pending transmission to be
flushed.
CLKS
— Clock Select (Bit 6)
The nominal BDLC operating frequency (mux interface clock
frequency - f
bdlc
) must always be 1.048576 MHz or 1 MHz in order for
J1850 bus communications to take place properly. The CLKS register
bit is provided to allow the user to indicate to the BDLC which
frequency (1.048576 MHz or 1 MHz) is used so that each symbol time
can be automatically adjusted.
The CLKS bit is a write once bit. All writes to this bit will be ignored
after the first one.
1 = Binary frequency (1.048576 MHz) is used for f
bdlc
.
0 = Integer frequency (1 MHz) is used. for f
bdlc
J1850 VPW Valid/Invalid Bits & Symbols describes the transmitter
and receiver VPW symbol timing for integer and binary frequencies.
IE
— Interrupt Enable (Bit 1)
This bit determines whether the BDLC will generate CPU interrupt
requests. It does not
affect CPU interrupt requests when exiting the
BDLC Stop or Wait modes. Interrupt requests will be maintained until
all of the interrupt request sources are cleared, by performing the
specified actions upon the BDLC’s registers. Interrupts that were
pending at the time that this bit is cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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