Datasheet

Byte Data Link Controller Module
Register Descriptions
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Register Descriptions
NOTE: All bits of all registers in this module are completely synchronous to
internal clocks during a register read.
BDLC Control
Register 1
(DLCBCR1)
This register is used to configure and control the BDLC.
READ: any time
WRITE: IMSG, IE, and WCM any time.
CLKS write once in normal and emulation modes.
CLKS bit has modified functionality in special test mode.
Writes to unimplemented bits 5-2 are ignored.
IMSG — Ignore Message (Bit 7)
This bit allows the CPU to ignore messages by disabling updates of
the DLCBSVR register until a new Start of Frame (SOF) or a BREAK
symbol is detected. BDLC transmitter and receiver operation are
unaffected by the state of the IMSG bit.
1 = Disable DLCBSVR Updates. When set, all BDLC interrupt
sources (exceptions are described below) will be prevented
from updating DLCBSVR status bits. Setting IMSG does not
clear pending interrupt flags, the behavior of which will still be
as described in BDLC State Vector Register (DLCBSVR). If
this bit is set while the BDLC is receiving or transmitting a
message, state vector register updates will be inhibited for the
rest of the message.
Address Offset: $0000
Bit 7 654321Bit 0
Read:
IMSG CLKS
0000
IE WCM
Write:
Reset: 11000000
= Unimplemented
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