Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
IP Bus Interface
Figure 126 BDLC Block Diagram - IP Bus Interface
The IP Bus Interface provides the interface between the IP Bus and the
rest of the BDLC. The address space of the BDLC is continuous,
consisting of 8 bytes starting at the base address. The base address of
the module is hardware programmable as defined by the IP Bus
Specification.
The register decode map is fixed and begins at the first address of the
Module Base Address. Table 107 in Register Map shows the registers
associated with the BDLC module and their relative offset from the base
address.
To IP Bus
Protocol Handler
MUX Interface
IP Bus Interface
Rx/Tx
Buffers
Physical Interface
To J1850 Bus
BDLC
Port Integration Module
BDLC Core
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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