Datasheet

Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
contains an indefinite number of data bytes. All of the other features of
the frame remain the same, including the SOF, CRC, and EOD symbols.
Another node wishing to send a Block Mode transmission must first
inform all other nodes on the network that this is about to happen. This
is usually accomplished by sending a special predefined message.
Transmitting a
Message in Block
Mode
A Block mode message is transmitted inherently by simply loading the
bytes one by one into the BDR register until the message is complete.
The programmer should wait until the TDRE flag is set prior to writing a
new byte of data into the BDR register. The BDLC does not contain any
predefined maximum J1850 message length requirement.
J1850 Bus Errors The BDLC detects several types of transmit and receive errors which
can occur during the transmission of a message onto the J1850 bus.
Transmission Error If the BDLC is transmitting a message and the message received
contains a symbol error, a framing error, a bus fault, a BREAK symbol,
or a logic ‘1’ symbol when a logic “0” is being transmitted, this constitutes
a transmission error. Receiving a logic ‘0’ symbol when transmitting a
logic ‘1’ is considered a loss of arbitration condition (See section
Message Arbitration) and not a transmission error. When a transmission
error is detected the BDLC will immediately cease transmitting. Further
transmission or reception will be disabled until a valid EOF symbol is
detected on the J1850 bus. The error condition is reflected by setting the
symbol invalid or out of range flag in the DLCBSVR register. If the
interrupt enable bit (IE in DLCBCR1) is set, an interrupt request from the
BDLC is generated. Reading the DLCBSVR register will clear this flag.
CRC Error A cyclical redundancy check (CRC) error is detected when the data
bytes and CRC byte of a received message are processed, and the CRC
calculation result is not equal to $C4.The CRC code should detect any
single and 2 bit errors, as well as all 8 bit burst errors, and almost all
other types of errors. The CRC error flag (in DLCBSVR) is set when a
CRC error is detected. If the interrupt enable bit (IE in DLCBCR1) is set,
an interrupt request from the BDLC is generated. Reading the
DLCBSVR register will clear this flag.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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