Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Byte Data Link
MC9S12DP256 — Revision 1.1
Byte Data Link Controller Module
Figure 125 BDLC Protocol Handler Outline
Rx & Tx Shift
Registers
The Rx Shift Register gathers received serial data bits from the J1850
bus and makes them available in parallel form to the Rx Shadow
Register. The Tx Shift Register takes data, in parallel form, from the Tx
Shadow Register and presents it serially to the State Machine so that it
can be transmitted onto the J1850 bus.
Rx Shift Register
To IP Bus Interface & Rx/Tx Buffer’s
State Machine
To Pad Drivers
Rx Data
Tx Data
Control
8
Tx Shift Register
TxP
DIGITAL FILTER IN
Control
8
Rx Shadow Register Tx Shadow Register
Loopback
RxP
loopback
control
TxP
Multiplexer
DLOOP from BCR2
BDLC
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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